H8SXSLASH1663R datasheet(774/1504 Pages) RENESAS

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Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 742 of 1468

REJ09B0412-0200

14.4.4

Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit

counter.

This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of

TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR.

Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.

Table 14.31 shows the register combinations used in cascaded operation.

Note:

When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid

and the counter operates independently in phase counting mode.

Table 14.31 Cascaded Combinations

Combination

Upper 16 Bits

Lower 16 Bits

Channels 1 and 2

TCNT_1

TCNT_2

Channels 4 and 5

TCNT_4

TCNT_5

(1)

Example of Cascaded Operation Setting Procedure

Figure 14.18 shows an example of the setting procedure for cascaded operation.

Cascaded operation

Set cascading

Start count

Set bits TPSC2 to TPSC0 in the channel 1

(channel 4) TCR to B'1111 to select TCNT_2

(TCNT_5) overflow/underflow counting.

Set the CST bit in TSTR for the upper and lower

channels to 1 to start the count operation.

[1]

[2]

[1]

[2]

Figure 14.18 Cascaded Operation Setting Procedure

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