H8SXSLASH1663R datasheet(775/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

Scroll/Zoom	100%

Hersteller	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

775 / 1504 page

Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 743 of 1468

REJ09B0412-0200

(2)

Examples of Cascaded Operation

Figure 14.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been

set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the

TIOC pin rising edge has been selected.

When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of

the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.

TCNT_2

clock

TCNT_2

H'FFFF

H'0000

H'0001

TIOCA1,

TIOCA2

TGRA_1

H'03A2

TGRA_2

H'0000

TCNT_1

clock

TCNT_1

H'03A1

H'03A2

Figure 14.19 Example of Cascaded Operation (1)

Figure 14.20 illustrates the operation when counting upon TCNT_2 overflow/underflow has been

set for TCNT_1, and phase counting mode has been designated for channel 2.

TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.

TCLKC

TCNT_2

FFFD

TCNT_1

0001

TCLKD

FFFE

FFFF

0000

0001

0002

0001

0000

FFFF

0000

Figure 14.20 Example of Cascaded Operation (2)

H8SX/1663R Datenblatt(PDF) 775 Page - Renesas Technology Corp

H8SX/1663R Datenblatt(HTML) 775 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL