H8SXSLASH1663R datasheet(776/1504 Pages) RENESAS

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Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 744 of 1468

REJ09B0412-0200

14.4.5

PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0-, 1-, or toggle-output can be

selected as the output level in response to compare match of each TGR.

Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty cycle.

Designating TGR compare match as the counter clearing source enables the cycle to be set in that

also possible.

There are two PWM modes, as described below.

1. PWM mode 1

PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and

TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR

are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The

outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare

matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If

the set values of paired TGRs are identical, the output value does not change when a compare

match occurs.

In PWM mode 1, a maximum 8-phase PWM output is possible.

2. PWM mode 2

PWM output is generated using one TGR as the cycle register and the others as duty cycle

registers. The output specified in TIOR is performed by means of compare matches. Upon

counter clearing by a synchronous register compare match, the output value of each pin is the

initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the

output value does not change when a compare match occurs.

In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with

synchronous operation.

The correspondence between PWM output pins and registers is shown in table 14.32.

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