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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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H8SX/1663R Datenblatt(PDF) 829 Page - Renesas Technology Corp |
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H8SX/1663R Datenblatt(HTML) 829 Page - Renesas Technology Corp |
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829 / 1504 page  Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Sep. 24, 2008 Page 797 of 1468 REJ09B0412-0200 15.4 Operation Figure 15.3 shows a schematic diagram of the PPG. PPG pulse output is enabled when the corresponding bits in NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match. Output trigger signal Pulse output pin Internal data bus Normal output/inverted output C PODR QD NDER Q NDR QD Figure 15.3 Schematic Diagram of PPG 15.4.1 Output Timing If pulse output is enabled, the NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 15.4 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. TCNT N N + 1 P φ TGRA N Compare match A signal NDRH mn PODRH PO8 to PO15 n m n Figure 15.4 Timing of Transfer and Output of NDR Contents (Example) |
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