H8SXSLASH1663M datasheet(459/1504 Pages) RENESAS

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Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 427 of 1468

REJ09B0412-0200

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DTIF Bit in DMDR

The DTIF bit in DMDR is set to 1 after the total transfer size of transfers is completed. When both

the DTIF and DTIE bits in DMDR are set to 1, a transfer end interrupt by the transfer counter is

requested to the CPU or DTC.

The DTIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus

cycle is completed.

The DTIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is

resumed by setting the DTE bit to 1 during interrupt handling.

For details on interrupts, see section 10.8, Interrupt Sources.

10.5.8

Priority of Channels

The channels of the DMAC are given following priority levels: channel 0 > channel 1 >

channel 2 > channel3. Table 10.6 shows the priority levels among the DMAC channels.

Table 10.6

Priority among DMAC Channels

Channel

Priority

Channel 0

Channel 1

Channel 2

High

Channel 3

Low

The channel having highest priority other than the channel being transferred is selected when a

transfer is requested from other channels. The selected channel starts the transfer after the channel

being transferred releases the bus. At this time, when a bus master other than the DMAC requests

the bus, the cycle for the bus master is inserted.

In a burst transfer or a block transfer, channels are not switched.

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