H8SXSLASH1663M datasheet(475/1504 Pages) RENESAS

475 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 443 of 1468

REJ09B0412-0200

(5)

Activation Timing by

DREQ Low Level with NRD = 1

When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is

delayed for one cycle.

Figure 10.38 shows an example of single address mode activated by the

DREQ signal low level

with NRD = 1.

The

DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately

after the DTE bit write cycle.

When a low level of the

DREQ signal is detected while a transfer request by the DREQ signal is

enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer

request is cleared. Receiving the next transfer request resumes after one cycle of the transfer

request duration inserted by NRD = 1 on completion of the single cycle and then a low level of the

DREQ signal is detected. This operation is repeated until the transfer is completed.

Min. of 3 cycles

DMA single

cycle

DMA single

cycle

DREQ

Address bus

Channel

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[1]

After DMA transfer request is enabled, a low level of the

DREQ signal is detected at the rising edge of the Bφ signal and a transfer

request is held.

[2][5] The DMAC is activated and the transfer request is cleared.

[3][6] A DMA cycle is started.

[4][7] Transfer request enable is resumed one cycle after completion of the single cycle.

(A low level of the

DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)

Transfer source/

Transfer destination

Bus

released

Bus

released

Transfer request

enable resumed

Transfer request

enable resumed

Transfer source/

Transfer destination

Request

Duration of transfer

request disabled

Duration of transfer

request disabled

Duration of transfer request

disabled which is extended

by NRD

Duration of transfer request

disabled which is extended

by NRD

Bus

released

Figure 10.38 Example of Transfer in Single Address Mode Activated

DREQ Low Level with NRD = 1

H8SX/1663M Datenblatt(PDF) 475 Page - Renesas Technology Corp

H8SX/1663M Datenblatt(HTML) 475 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL