H8SXSLASH1663M datasheet(476/1504 Pages) RENESAS

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Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 444 of 1468

REJ09B0412-0200

10.6

DMA Transfer End

Operations on completion of a transfer differ according to the transfer end condition. DMA

transfer completion is indicated that the DTE and ACT bits in DMDR are changed from 1 to 0.

(1)

Transfer End by DTCR Change from 1, 2, or 4, to 0

When DTCR is changed from 1, 2, or 4 to 0, a DMA transfer for the channel is completed. The

DTE bit in DMDR is cleared to 0 and the DTIF bit in DMDR is set to 1. At this time, when the

DTIE bit in DMDR is set to 1, a transfer end interrupt by the transfer counter is requested. When

the DTCR value is 0 before the transfer, the transfer is not stopped.

(2)

Transfer End by Transfer Size Error Interrupt

When the following conditions are satisfied while the TSEIE bit in DMDR is set to 1, a transfer

size error occurs and a DMA transfer is terminated. At this time, the DTE bit in DMDR is cleared

to 0 and the ESIF bit in DMDR is set to 1.

• In normal transfer mode and repeat transfer mode, when the next transfer is requested while a

transfer is disabled due to the DTCR value less than the data access size

• In block transfer mode, when the next transfer is requested while a transfer is disabled due to

the DTCR value less than the block size

When the TSEIE bit in DMDR is cleared to 0, data is transferred until the DTCR value reaches 0.

A transfer size error is not generated. Operation in each transfer mode is shown below.

• In normal transfer mode and repeat transfer mode, when the DTCR value is less than the data

access size, data is transferred in bytes

• In block transfer mode, when the DTCR value is less than the block size, the specified size of

data in DTCR is transferred instead of transferring the block size of data. The transfer is

performed in bytes.

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