H8SXSLASH1663M datasheet(498/1504 Pages) RENESAS

498 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 466 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

value

R/W

Description

DTE

R/W

Data Transfer Enable

Enables or disables data transfer on the corresponding

channel. When this bit is set to 1, this indicates that an

EXDMA operation is in progress.

When auto-request mode is specified, transfer

processing begins when this bit is set to 1. With

external requests, transfer processing begins when a

transfer request is issued after this bit has been set to

1. When this bit is cleared to 0 during an EXDMA

operation, transfer is halted.

If this bit is cleared to 0 during an EXDMA operation in

block transfer mode, this bit is cleared to 0 on

completion of the currently executing one-block

transfer. When this bit is cleared to 0 during an EXDMA

operation in cluster transfer mode, this bit is cleared to

0 on completion of the currently executing one-cluster

transfer.

If an external source that ends (aborts) transfer occurs,

this bit is automatically cleared to 0 and transfer is

terminated.

Do not change the operating mode, transfer method, or

other parameters while this bit is set to 1.

0: Data transfer disabled

1: Data transfer enabled (during an EXDMA operation)

[Clearing conditions]

•

When transfer of the total transfer size specified

ends

•

When operation is halted by a repeat size end

interrupt

•

When operation is halted by an extended repeat

area overflow interrupt

•

When operation is halted by a transfer size error

interrupt

•

When 0 is written to terminate transfer

In block transfer mode, the value written is effective

after one-block transfer ends.

In cluster transfer mode, the value written is

effective after one-cluster transfer ends.

•

When an address error or NMI interrupt occurs

•

Reset, hardware standby mode

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