H8SXSLASH1663M datasheet(502/1504 Pages) RENESAS

502 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 470 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

value

R/W

Description

MDS1

MDS0

R/W

Transfer Mode Select 1 and 0

Selects the transfer mode.

00: Normal transfer mode

01: Block transfer mode

10: Repeat transfer mode

11: Cluster transfer mode

TSEIE

R/W

Transfer Size Error Interrupt Enable

Enables or disables a transfer size error interrupt

request.

When this bit is set to 1 and the transfer counter value

becomes smaller than the data access size for one

transfer request by EXDMAC transfer, the DTE bit is

cleared to 0 by the next transfer request. At the same

time, the ESIF bit is set to 1 to indicate that a transfer

size error interrupt request is generated.

When cluster transfer read/write address mode is

specified, this bit should be set to 1.

Transfer size error interrupt request occurs in the

following conditions:

• In normal transfer and repeat transfer modes, the

total transfer size set in EDTCR is smaller than the

data access size

• In block transfer mode, the total transfer size set in

EDTCR is smaller than the block size

• In cluster transfer mode, the total transfer size set in

EDTCR is smaller than the cluster size

0: Transfer size error interrupt request disabled

1: Transfer size error interrupt request enabled



Reserved

They are always read as 0 and cannot be modified.

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