ADE5166ASTZF62 datasheet(82/148 Pages) AD

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ADE5166/ADE5169

Rev. 0 | Page 82 of 148

Mnemonic

Description

Bytes

Cycles

JNC rel

Jump on carry = 0

JZ rel

Jump on accumulator = 0

JNZ rel

Jump on accumulator ≠ 0

DJNZ Rn, rel

Decrement register, JNZ relative

LJMP

Long jump unconditional

LCALL addr16

Long jump to subroutine

JB bit, rel

Jump on direct bit = 1

JNB bit, rel

Jump on direct bit = 0

JBC bit, rel

Jump on direct bit = 1 and clear

CJNE A, dir, rel

Compare A, direct JNE relative

CJNE A, #data, rel

Compare A, immediate JNE relative

CJNE Rn, #data, rel

Compare register, immediate JNE relative

CJNE @Ri, #data, rel

Compare indirect, immediate JNE relative

DJNZ dir, rel

Decrement direct byte, JNZ relative

Miscellaneous

NOP

No operation

READ-MODIFY-WRITE INSTRUCTIONS

Some 8052 instructions read the latch and others read the pin.

The state of the pin is read for instructions that input a port bit.

Instructions that read the latch rather than the pins are the ones

that read a value, possibly change it, and rewrite it to the latch.

Because these instructions involve modifying the port, it is

assumed that the pins being modified are outputs, so the output

state of the pin is read from the latch. This prevents a possible

misinterpretation of the voltage level of a pin. For example, if a

port pin is used to drive the base of a transistor, a 1 is written to

the bit to turn on the transistor. If the CPU reads the same port

bit at the pin rather than the latch, it reads the base voltage of

the transistor and interprets it as Logic 0. Reading the latch

rather than the pin returns the correct value of 1.

The instructions that read the latch rather than the pins are

called read-modify-write instructions and are listed in Table 68.

When the destination operand is a port or a port bit, these

instructions read the latch rather than the pin.

Table 68. Read-Modify-Write Instructions

Instruction

Example

Description

ANL

ANL P0, A

Logic AND

ORL

ORL P1, A

Logic OR

XRL

XRL P2, A

Logic XOR

JBC

JBC P1.1, LABEL

Jump if Bit = 1 and clear bit

CPL

CPL P2.0

Complement bit

INC

INC P2

Increment

DEC

DEC P2

Decrement

DJNZ

DJNZ P0, LABEL

Decrement and jump if not zero

MOV PX.Y, C1

MOV P0.0, C

Move carry to Bit Y of Port X

CLR PX.Y1

CLR P0.0

Clear Bit Y of Port X

SETB PX.Y1

SETB P0.0

Set Bit Y of Port X

1 These instructions read the port byte (all eight bits), modify the addressed

bit, and write the new byte back to the latch.

INSTRUCTIONS THAT AFFECT FLAGS

Many instructions explicitly modify the carry bit, such as the

MOV C bit and CLR C instructions. Other instructions that

affect status flags are listed in this section.

ADD A, Source

This instruction adds the source to the accumulator. No status

flags are referenced by the instruction.

Table 69. ADD A (Source) Affected Status Flags

Flag

Description

Set if there is a carry out of Bit 7. Cleared otherwise. Used

to indicate an overflow if the operands are unsigned.

Set if there is a carry out of Bit 6 or a carry out of Bit 7, but

not if both are set. Used to indicate an overflow for

signed addition. This flag is set if two positive operands

yield a negative result or if two negative operands yield a

positive result.

Set if there is a carry out of Bit 3. Cleared otherwise.

ADDC A, Source

This instruction adds the source and the carry bit to the accu-

mulator. The carry status flag is referenced by the instruction.

Table 70. ADDC A (Source) Affected Status Flags

Flag

Description

Set if there is a carry out of Bit 7. Cleared otherwise. Used

to indicate an overflow if the operands are unsigned.

Set if there is a carry out of Bit 6 or a carry out of Bit 7, but

not if both are set. Used to indicate an overflow for

signed addition. This flag is set if two positive operands

yield a negative result or if two negative operands yield a

positive result.

Set if there is a carry out of Bit 3. Cleared otherwise.

ADE5166ASTZF62 Datenblatt(PDF) 82 Page - Analog Devices

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