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ADE5166ASTZF62 Datenblatt(PDF) 25 Page - Analog Devices

Teilenummer ADE5166ASTZF62
Bauteilbeschribung  Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
PDF  148 Pages
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ADE5166ASTZF62 Datenblatt(HTML) 25 Page - Analog Devices

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ADE5166/ADE5169
Rev. 0 | Page 25 of 148
Table 17. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8)
Bit
Bit Address
Mnemonic
Default
Description
7
0xFF
FPSR
0
Power supply restored interrupt flag. Set when the VDD power supply has been restored.
This occurs when the source of VSWOUT changes from VBAT to VDD.
6
0xFE
FPSM
0
PSM interrupt flag. Set when an enabled PSM interrupt condition occurs.
5
0xFD
FSAG
0
Voltage SAG interrupt flag. Set when an ADE energy measurement SAG condition occurs.
4
0xFC
Reserved
0
This bit must be kept at 0 for proper operation.
3
0xFB
FVADC
0
VDCINADC monitor interrupt flag. Set when VDCIN changes by VDCIN_DIFF or when VDCIN
measurement is ready.
2
0xFA
FBAT
0
VBAT monitor interrupt flag. Set when VBAT falls below BATVTH or when VBAT measurement is
ready.
1
0xF9
FBSO
0
Battery switchover interrupt flag. Set when VSWOUT switches from VDD to VBAT.
0
0xF8
FVDCIN
0
VDCIN monitor interrupt flag. Set when VDCIN falls below 1.2 V.
Table 18. Battery Switchover Configuration SFR (BATPR, Address 0xF5)
Bit
Mnemonic
Default
Description
[7:2]
Reserved
0
These bits must be kept at 0 for proper operation.
[1:0]
BATPRG
0
Control bits for battery switchover.
BATPRG
Result
00
Battery switchover enabled on low VDD
01
Battery switchover enabled on low VDD and low VDCIN
1X
Battery switchover disabled
Table 19. Peripheral Configuration SFR (PERIPH, Address 0xF4)
Bit
Mnemonic
Default
Description
7
RX2FLAG
0
If set, indicates that an RxD2 edge event triggered wake-up from PSM2.
6
VSWSOURCE
1
Indicates the power supply that is internally connected to VSWOUT (0 VSWOUT = VBAT, 1 VSWOUT = VDD).
5
VDD_OK
1
If set, indicates that VDD power supply is ready for operation.
4
PLL_FLT
0
If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit (see Table 51) in
the start ADC measurement SFR (ADCGO, Address 0xD8) to acknowledge the fault and clear the
PLL_FLT bit.
3
REF_BAT_EN
0
Set this bit to enable internal voltage reference in PSM2 mode. This bit should be set if LCD is on in
PSM1 and PSM2 mode.
2
Reserved
0
This bit must be kept at 0 for proper operation.
[1:0]
RXPROG
0
Controls the function of the P0.7/SS/T1/RxD2 pin.
RXPROG
Result
00
GPIO
01
RxD2 with wake-up disabled
11
RxD2 with wake-up enabled
Table 20. Power Management Interrupt Enable SFR (IPSME, Address 0xEC)
Bit
Mnemonic
Default
Description
7
EPSR
0
Enables a PSM interrupt when the power supply restored interrupt flag (FPSR) is set.
6
Reserved
0
Reserved.
5
ESAG
0
Enables a PSM interrupt when the voltage SAG interrupt flag (FSAG) is set.
4
Reserved
0
This bit must be kept at 0 for proper operation.
3
EVADC
0
Enables a PSM interrupt when the VDCINADC monitor interrupt flag (FVADC) is set.
2
EBAT
0
Enables a PSM interrupt when the VBAT monitor interrupt flag (FBAT) is set.
1
EBSO
0
Enables a PSM interrupt when the battery switchover interrupt flag (FBSO) is set.
0
EVDCIN
0
Enables a PSM interrupt when the VDCIN monitor interrupt flag (FVDCIN) is set.
Table 21. Scratch Pad 1 SFR (SCRATCH1, Address 0xFB)
Bit
Mnemonic
Default
Description
7 to 0
SCRATCH1
0
Value can be written/read in this register. This value is maintained in all the power saving modes.



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