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CDC921 Datenblatt(PDF) 13 Page - Texas Instruments |
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CDC921 Datenblatt(HTML) 13 Page - Texas Instruments |
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13 / 17 page ![]() CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS623 –MAY 27, 1999 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued) PCI PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT ten1 Output enable time SEL133/100 PCIx f(PCI) = 33 MHz 6 10 ns tdis1 Output disable time SEL133/100 PCIx f(PCI) = 33 MHz 8 10 ns tc PCIx clock period† f(PCI) = 33 MHz 30 30.12 30.5 ns Cycle to cycle jitter f(CPU) = 100 or 133 MHz 300 ps Duty cycle f(PCI) = 33 MHz 45 55 % tsk(o) PCIx bus skew PCIx PCIx f(PCI) = 33 MHz 70 300 ps tsk(p) PCIx pulse skew PCIn PCIn f(PCI) = 33 MHz 4 ns t(off) PCIx clock to 3V66 clock offset –1.2 –3 ns tw1 Pulse duration width, high f(PCI) = 33 MHz 12 ns tw2 Pulse duration width, low f(PCI) = 33 MHz 12 ns tr Rise time VO = 0.4 V to 2 V 0.5 1.6 2 ns tf Fall time VO = 0.4 V to 2 V 0.5 1.5 2 ns † The average over any 1- µs period of time is greater than the minimum specified period. |
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