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TSB12C01APZ Datenblatt(PDF) 37 Page - Texas Instruments |
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TSB12C01APZ Datenblatt(HTML) 37 Page - Texas Instruments |
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37 / 59 page ![]() 4–7 4.5 CycleMark The format of the CycleMark data is shown in Figure 4–8. The receiver module inserts a single quadlet to mark the end of an isochronous cycle. The quadlet is inserted into the receive-FIFO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CyDne Figure 4–8. CycleMark Format Table 4–8. CycleMark Functions FIELD NAME DESCRIPTION CyDne This field indicates the end of an isochronous cycle. 4.6 Phy Configuration The format of the phy configuration packet is shown in Figure 4–9. The phy configuration packet transmit contains two quadlets, which are loaded into the ATF. The first quadlet is written to address 80h. The second quadlet is written to address 8Ch. The 00E0h in the first quadlet tells the TSB12C01A that this is the phy configuration packet. The Eh is then replaced with 0h before the packet is transmitted to the phy interface. There is a possibility of a false header error on receipt of a phy configuration packet. If the first 16 bits of a phy configuration packet (see Figure 4–9) happen to match the destination identifier of a node (bus number and node number), the TSB12C01A on that node issues a header error since the node misinterprets the phy configuration packet as a data packet addressed to the node. The suggested solution to this potential problem is to assign bus numbers that all have the MS bit set to 1. Since the all-ones case is reserved for addressing the local bus, this leaves only 511 available unique bus identifiers. This is an artifact of the IEEE 1394-1995 standard. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 logical inverse of first 16 bits of first quadlet root_ID gap_cnt 00 RT 11 1 0 00 0 0 0 0 00 00 0 0 11 1 1 11 1 1 1 1 11 11 1 1 Figure 4–9. Phy Configuration Format |
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