TSB12C01APZ datasheet(26/59 Pages) TI

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3–10

3.2.10

ITF Status Register

The ITF status register allows access to the registers that control or monitor the ITF. The register is at

address 34h. All the FIFO flag bits are read only, and the FIFO control bits are read/write. Its initial value

is 0000_0000h.

Table 3–10. ITF Status Register

BITS

ACRONYM

FUNCTION NAME

DESCRIPTION

Full

ITF full flag

When Full is set, the FIFO is full and all writes are ignored.

AlF

ITF almost-full flag

When AlF is set, the FIFO can accept only one more write.

2–3

Reserved

4AV

ITF-4-available flag

When 4AV is set, the FIFO has space for at least four more quadlets.

5–13

Reserved

AlE

ITF-almost-empty flag

When AlE is set, the FIFO has only one quadlet in it.

Empty

ITF-empty flag

When Empty is set, the FIFO is empty.

16 – 18

Reserved

Clr

ITF-clear control bit

When Clr is set by software/firmware, the FIFO is cleared of all

entries.

20 – 22

Reserved

23 – 31

Size

ITF-size control bits

The size is equal to the ITF size number in quadlets.

3.2.11

GRF Status Register

The GRF status register allows access to the registers that control or monitor the GRF. The register is at

address 3Ch. All the FIFO flag bits are read only, and the FIFO control bits are read/write. Its initial value

is 0000_0000h.

Table 3–11. GRF Status Register

BITS

ACRONYM

FUNCTION NAME

DESCRIPTION

Full

GRF full flag

When Full is set, the FIFO is full.

AlF

GRF-almost-full flag

When AlF is set, the FIFO can accept only one more write.

2–11

Reserved

4Th

GRF four there

When 4Th is set, the FIFO has at least four quadlets in it.

Reserved

AlE

GRF-almost-empty

flag

When AlE is set, the FIFO has one quadlet in it.

Empty

GRF-empty flag

When Empty is set, the FIFO is empty and reads are ignored.

GRF control bit

This is the control bit for the GRF. When cd is set, either the first

quadlet of a packet is being read from the GRF_Data address, or the

final quadlet (trailer quadlet) of a packet is being read from the GRF

data address. See Section 4 for descriptions of received packet

formats.

17 – 18

Reserved

Clr

GRF-clear control bit

When Clr is set by software/firmware, the FIFO is cleared of all

entries.

20 – 22

Reserved

23 – 31

Size

GRF-size control bits

The size is equal to the GRF size number in quadlets.

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