T15L256A datasheet(1/10 Pages) TMT

Teilenummer	T15L256A

Bauteilbeschribung	32K X 8 LOW POWER CMOS STATIC RAM???

PDF	10 Pages

Scroll/Zoom	100%

Hersteller	TMT [Taiwan Memory Technology]

Direct Link	http://www.tmtech.com.tw

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1 / 10 page

TE

CH

tm

T15L256A

Taiwan Memory Technology, Inc. reserves the right

P. 1

Publication Date: APR. 2001

to change products or specifications without notice.

Revision:C

SRAM

32K X 8 LOW POWER

CMOS STATIC RAM

FEATURES

• Access time: 35ns/70ns

• Low power consumption : Active 200 mW(typ.)

• Low operating current : 50mA

• Single + 3.3V power supply

• Fully static operation – No clock or refreshing

required

• All inputs and outputs directly LVTTL compatible

• Common I/O capability

• Available packages : 28-pin 300 mil SOJ, 28-pin

SOP, TSOP-I (forward type ).

• Output enable (OE ) available for very fast access

PIN CONFIGURATION

A12

A14

A7

A6

A5

A3

A4

A2

A1

A0

I/O1

I/O2

I/O3

Vss

28

27

26

25

23

24

22

21

20

19

18

17

16

15

1

2

3

4

6

5

7

8

9

10

11

12

13

14

Vcc

A13

A8

A9

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

WE

OE

CS

SOJ

&

SOP

GENERAL DESCRIPTION

The T15L256A is a high speed, low power

CMOS static RAM organized as 32,768 x 8 bits that

operates on a single 3.3-volt power supply.

This

device is packaged in standard 28-pin 300 mil SOJ ,

28-pin SOP, TSOP-I forward.

BLOCK DIAGRAM

DECODER

CONTROL

A0

→

A14

→

CS

→

OE

→

WE

→

← I / O 1

← I / O8

Vcc

→

DATA I/O

CORE

ARRAY

→

Vss

.

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A14

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

CS

Chip Select Inputs

WE

Write Enable

OE

Output Enable

Vcc

Power Supply

Vss

Ground

PART NUMBER EXAMPLES

PACKAGE

SPEED

T15L256A-35J

SOJ

35ns

T15L256A-70P

TSOP-I

70ns

T15L256A-70D

SOP

70ns

TSOP-I

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

OE

A11

A9

A8

A13

WE

VCC

A14

A12

A7

A6

A5

A4

A3

A10

CS

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

A0

A1

A2

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