T15M256A datasheet(7/10 Pages) TMT

Teilenummer	T15M256A

Bauteilbeschribung	32K X 8 LOW POWER CMOS STATIC RAM????

PDF	10 Pages

Scroll/Zoom	100%

Hersteller	TMT [Taiwan Memory Technology]

Direct Link	http://www.tmtech.com.tw

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7 / 10 page

T15M256A

Taiwan Memory Technology, Inc. reserves the right

P. 7

Publication Date: APR. 2001

to change products or specifications without notice.

Revision: C

Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs

should not be applied.

2. The data output from D

OUT are the same as the data written to

IN during the write cycle.

3. D

OUT provides the read data for the next address.

4. Transition is measured

± 500 mV from steady state with C

L = 5pF.

This parameter is

guaranteed but not 100% tested.

5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of

tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the

required tDW.

If OE is high during a WE controlled write cycle, this requirement does not

apply and the write pulse can be as short as the specified tWP.

T15M256A Datenblatt(PDF) 7 Page - Taiwan Memory Technology