6

October 2002

SPT7750

OPERATION

The SPT7750 has 256 preamp/comparator pairs which

equally by the resistive ladder as shown in the block dia-

gram. This voltage is applied to the positive input of each

preamplifier/comparator pair. An analog input voltage ap-

preamplifier/comparator pair. The comparators are then

clocked through each one’s individual clock buffer. When

the CLK pin is in the low state, the master or input stage of

the comparators compare the analog input voltage to the

respective reference voltage. When the CLK pin changes

from low to high the comparators are latched to the state

prior to the clock transition and output logic codes in se-

down to the point where the magnitude of the input signal

changes sign (thermometer code). The output of each

comparator is then registered into four 64-to-6 bit decod-

ers when the CLK is changed from high to low. At the out-

put of the decoders is a set of four 7-bit latches which are

enabled (“track”) when the clock changes from high to low.

From here, the output of the latches are coded into 6 LSBs

from 4 columns and 4 columns are coded into 2 MSBs.

Finally, 8 ECL output latches and buffers are used to drive

the external loads. The conversion takes one clock cycle

from the input to the data outputs.

Figure 2 – Timing Diagram

CLK

CLK

DRA

DRA

DRB

DRB

Data Bank B

N-1

N+1

N+3

N

N+1

N+2

N+3

N+4

N+5

N+6

N-2

N

N+2

N+4

1.75 ns

typ

1.4 ns

typ

Data Bank A

2.0 ns

1.75 ns

typ

1.4 ns

typ