SPT7750

8-BIT, 500 MSPS, FLASH A/D CONVERTER

OCTOBER 2002

FEATURES

• 1:2 Demuxed ECL compatible outputs

• Wide input bandwidth – 900 MHz

•Low input capacitance – 15 pF

• Metastable errors reduced to 1 LSB

• Monolithic for low cost

•Gray code output

APPLICATIONS

• Digital oscilloscopes

•Transient capture

• Radar, EW, ECM

• Direct RF down-conversion

GENERAL DESCRIPTION

The SPT7750 is a full parallel (flash) analog-to-digital con-

verter capable of digitizing full scale (0 to –2 V) inputs into

eight-bit digital words at an update rate of 500 MSPS. The

ECL-compatible outputs are demultiplexed into two sepa-

rate output banks, each with differential data ready out-

puts to ease the task of data capture. The SPT7750’s wide

input bandwidth and low capacitance eliminate the need

for external track-and-hold amplifiers for most applica-

tions. A proprietary decoding scheme reduces metastable

errors to the 1 LSB level. The SPT7750 operates from a

single –5.2 V supply, with a nominal power dissipation of

5.5 W.

The SPT7750 is available in an 80-lead surface-mount

MQuad package over the industrial temperature range

(–25 °C to +85 °C).

256

255

152

151

128

127

64

63

2

1

CLOCK

BUFFER

D0

(LSB)

D1

D2

D3

D4

D5

D6

D7

(MSB)

D8

(OVR)

Analog

Input

Preamp

Comparator

CLK CLK

D8B

D7B

D6B

D5B

D4B

D3B

D2B

D1B

D0B

D8A

D7A

D6A

D5A

D4A

D3A

D2A

D1A

D0A

D8B (OVR)

D7B (MSB)

D6B

D5B

D4B

D3B

D2B

D1B

D0B (LSB)

D8A (OVR)

D7A (MSB)

D6A

D5A

D4A

D3A

D2A

D1A

D0A (LSB)

DRA (DATA READY)

DRA (DATA READY)

DEMUX

CLOCK

BUFFER

DRB (DATA READY)

DRB (DATA READY)

BLOCK DIAGRAM