SRAM

SRAM

SRAM

SRAM

SRAM

MT5C2568

AS5C2568

MT5C2568 / AS5C2568

Rev. 4.5 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

1

Austin Semiconductor, Inc.

FEATURES

• Access Times: 12, 15, 20, 25, 35, 45, 55, 70, & 100ns

• Battery Backup: 2V data retention

• Low power standby

• High-performance, low-power CMOS double-metal process

• Single +5V (+10%) Power Supply

• Easy memory expansion with CE\

• All inputs and outputs are TTL compatible

OPTIONS

MARKING

• Timing

-12

-15

20ns access

-20

25ns access

-25

35ns access

-35

45ns access

-45

55ns access

2

-55

70ns access

2

-70

100ns access

-100

Ceramic DIP (300 mil)

C

No. 108

Ceramic DIP (600 mil)

CW

No. 110

Ceramic LCC (28 leads)

EC

No. 204

Ceramic LCC (32 leads)

ECW

No. 208

Ceramic Flat Pack

F

No. 302

Ceramic SOJ

DCJ

No. 500

• Operating Temperature Ranges

• 2V data retention/low power

L

NOTES:

1. -12 available in IT only.

2. Electrical characteristics identical to those provided for the

45ns access devices.

3. Plastic SOJ (DJ Package) is available on the AS5C2568 datasheet.

PIN ASSIGNMENT

(Top View)

AVAILABLE AS MILITARY

SPECIFICATIONS

•SMD 5962-88662

•SMD 5962-88552

•MIL-STD-883

28-PIN SOJ (DCJ)

28-Pin DIP (C, CW)

32-Pin LCC (ECW)

28-Pin Flat Pack (F)

28-Pin LCC (EC)

GENERAL DESCRIPTION

The Austin Semiconductor SRAM family employs

high-speed, low power CMOS designs using a four-transistor

memory cell. These SRAMs are fabricated using double-layer

metal, double-layer polysilicon technology.

For flexibility in high-speed memory applications,

Austin Semiconductor offers chip enable (CE\) and output

enable (OE\) capability. These enhancements can place the

outputs in High-Z for additional flexibility in system design.

Writing to these devices is accomplished when write

enable (WE\) and CE\ inputs are both LOW. Reading is

accomplished when WE\ remains HIGH and CE\ and OE\ go

LOW. The device offers a reduced power standby mode when

disabled. This allows system designs to achieve low standby

power requirements.

The “L” version provides a battery backup/low

voltage data retention mode, offering 2mW maximum power

dissipation at 2 volts. All devices operate from a single +5V

power supply and all inputs and outputs are fully TTL

compatible.

4 3 2 1 32 31 30

14 15 16 17 18 19 20

5

6

7

8

9

10

11

12

13

A6

A5

A4

A3

A2

A1

A0

NC

DQ1

29

28

27

26

25

24

23

22

21

A8

A9

A11

NC

OE\

A10

CE\

DQ8

DQ7

3 2 1 28 27

13 14 15 16 17

4

5

6

7

8

9

10

11

12

A6

A5

A4

A3

A2

A1

A0

DQ1

DQ2

26

25

24

23

22

21

20

19

18

A13

A8

A9

A11

OE\

A10

CE\

DQ8

DQ7

A14

1

A12

2

27 WE\

A7

3

26 A13

A6

4

25 A8

A5

5

24 A9

A4

6

23 A11

A3

7

22 OE\

A2

8

21 A10

A1

9

20 CE\

A0 10

19 DQ8

DQ1 11

18 DQ7

DQ2 12

17 DQ6

DQ3 13

16 DQ5

15 DQ4

32K x 8 SRAM

SRAM MEMORY ARRAY

For more products and information

please visit our web site at

www.austinsemiconductor.com

A14

1

28

A12

2

27

WE\

A7

3

26

A13

A6

4

25

A8

A5

5

24

A9

A4

6

23

A11

A3

7

22

OE\

A2

8

21

A10

A1

9

20

CE\

A0

10

19

DQ8

DQ1

11

18

DQ7

DQ2

12

17

DQ6

DQ3

13

16

DQ5

14

15

DQ4