AD6657EBZ datasheet(20/32 Pages) AD

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AD6657

Rev. 0 | Page 20 of 32

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR from the low frequency

SNR (SNRLF) at a given input frequency (fIN) due to jitter (tJRMS)

can be calculated by

SNRHF = −10log[(2π × fIN × tJRMS)2 + 10(−SNRLF/10) ]

In the equation, the rms aperture jitter represents the clock

input jitter specification. IF undersampling applications are

particularly sensitive to jitter, as illustrated in Figure 43.

100

INPUT FREQUENCY (MHz)

0.05ps

0.20ps

0.50ps

1.00ps

1.50ps

Figure 43. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases

in which aperture jitter may affect the dynamic range of the

AD6657. Power supplies for clock drivers should be separated

from the ADC output driver supplies to avoid modulating the

clock signal with digital noise. Low jitter, crystal-controlled

oscillators make the best clock sources. If the clock is generated

from another type of source (by gating, dividing, or another

method), it should be retimed by the original clock at the last

step. Refer to Application Note AN-501 and Application Note

AN-756 for more information about jitter performance as it

relates to ADCs (see www.analog.com).

POWER DISSIPATION AND STANDBY MODE

The power dissipated by the AD6657 is proportional to its clock

rate (see Figure 44). The digital power dissipation does not vary

significantly because it is determined primarily by the DRVDD

supply and the bias current of the LVDS drivers.

Reducing the capacitive load presented to the output drivers can

minimize digital power consumption. The data in Figure 44 was

taken using the same operating conditions as those used in the

Typical Performance Characteristics section, with a 5 pF load

on each output driver.

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

SAMPLING FREQUENCY (MSPS)

IAVDD

TOTAL POWER

IDRVDD

Figure 44. Power and Current vs. Sampling Frequency

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD6657 is placed in power-down

mode. In this state, the ADC typically dissipates 4.5 mW.

During power-down, the output drivers are placed in a high

impedance state. Asserting the PDWN pin low returns the

AD6657 to its normal operating mode. Note that PDWN is

referenced to the digital output driver supply (DRVDD) and

should not exceed that supply voltage.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and must be recharged when returning to

normal operation. As a result, wake-up time is related to the

time spent in power-down mode; shorter power-down cycles

result in proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map

CHANNEL/CHIP SYNCHRONIZATION

The AD6657 has a SYNC input that offers the user flexible syn-

chronization options for synchronizing the clock divider. The

clock divider sync feature is useful for guaranteeing synchronized

sample clocks across multiple ADCs.

The SYNC input is internally synchronized to the sample clock;

however, to ensure that there is no timing uncertainty between

multiple parts, the SYNC input signal should be externally syn-

chronized to the input clock signal, meeting the setup and hold

times shown in Table 5. The SYNC input should be driven using

a single-ended CMOS-type signal.

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