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ICS1893CF Datenblatt(PDF) 76 Page - Integrated Device Technology

Teilenummer ICS1893CF
Bauteilbeschribung  3.3-V 10Base-T/100Base-TX Integrated PHYceiver?
PDF  127 Pages
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Hersteller  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS1893CF Datenblatt(HTML) 76 Page - Integrated Device Technology

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ICS1893CF, Rev. J, 08/11/09
August, 2009
76
Chapter 7 Management Register Set
ICS1893CF Data Sheet - Release
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
7.12.9 Premature End (bit 17.5)
The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream
by the ICS1893CF.
During reception of a valid packet, the ICS1893CF examines each symbol to ensure that the data being
passed to the MAC Interface is error free. If two consecutive Idles are encountered, it indicates this
condition to the MAC by setting this bit.
If this bit is set to a logic:
Zero, it indicates a Premature End condition has not been detected since either the last read or reset of
this register.
One, it indicates a Premature End condition was detected in the packet since either the last read or reset
of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.)
Note: This bit has no definition in 10Base-T mode.
7.12.10 Auto-Negotiation Complete (bit 17.4)
The Auto-Negotiation Complete bit is used to indicate to an STA the completion of the Auto-Negotiation
process. When this bit is set to logic:
Zero, it indicates that the auto-negotiation process is either not complete or is disabled by the Control
Register’s Auto-Negotiation Enable bit (bit 0.12)
One, it indicates that the ICS1893CF has completed the auto-negotiation process and that the contents
of Management Registers 4, 5, and 6 are valid.
7.12.11 100Base-TX Signal Detect (bit 17.3)
The 100Base-TX Signal Detect bit indicates either the presence or absence of a signal on the Twisted-Pair
Receive pins (TP_RXP and TP_RXN) in 100Base-TX mode. This bit is logic:
Zero when no signal is detected on the Twisted-Pair Receive pins.
One when a signal is present on the Twisted-Pair Receive pins.
7.12.12 Jabber Detect (bit 17.2)
Bit 17.2 is functionally identical to bit 1.1. The Jabber Detect bit indicates whether a jabber condition has
occurred. This bit is a 10Base-T function.
7.12.13 Remote Fault (bit 17.1)
Bit 17.1 is functionally identical to bit 1.4.
7.12.14 Link Status (bit 17.0)
Bit 17.0 is functionally identical to bit 1.2.



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