ICS1893CF datasheet(92/127 Pages) IDT

92 / 127 page

ICS1893CF, Rev. J, 08/11/09

August, 2009

Chapter 8 Pin Diagram, Listings, and Descriptions

ICS1893CF Data Sheet - Release

RXD0

RXD1

RXD2

RXD3

Output

Receive Data 0–3.

• RXD0 is the least-significant bit and RXD3 is the most-significant bit of

the MII receive data nibble.

• While the ICS1893CF asserts RXDV, the ICS1893CF transfers the

receive data signals on the RXD0–RXD3 pins to the MAC Interface

synchronously on the rising edges of RXCLK.

RXDV

Output

Receive Data Valid.

The ICS1893CF asserts RXDV to indicate to the MAC that data is

available on the MII Receive Bus (RXD[3:0]). The ICS1893CF:

• Asserts RXDV after it detects and recovers the Start-of-Stream

delimiter, /J/K/. (For the timing reference, see Chapter 9.5.6,

“100M/MII Media Independent Interface: Synchronous Receive

Timing”.)

• De-asserts RXDV after it detects either the End-of-Stream delimiter

(/T/R/) or a signal error.

Note: RXDV is synchronous with the Receive Data Clock, RXCLK.

RXER

Output

Receive Error.

When the MAC Interface is in:

• 10M MII mode, RXER is not used.

• 100M MII mode, the ICS1893CF asserts a signal on the RXER pin

when either of the following two conditions are true:

– Errors are detected during the reception of valid frames

– A False Carrier is detected

Note:

1. An ICS1893CF asserts a signal on the RXER pin upon detection of a

False Carrier so that repeater applications can prevent the

propagation of a False Carrier.

2. The RXER signal always transitions synchronously with RXCLK.

3. The signal on RXER pin is conditioned by the RXTRI pin.

TXCLK

Output

Transmit Clock.

The ICS1893CF generates this clock signal to synchronize the transfer of

data from the MAC Interface to the ICS1893CF. When the mode is:

• 10Base-T, the TXCLK frequency is 2.5 MHz.

• 100Base-TX, the TXCLK frequency is 25 MHz.

Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued)

Name

Number

Type

Pin Description

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