ATmega328P datasheet(25/345 Pages) ATMEL

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7810A–AVR–11/09

ATmega328P [Preliminary]

System Clock and Clock Options

8.1

Clock Systems and their Distribution

Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules

not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 37. The clock systems are detailed below.

Figure 8-1.

Clock Distribution

8.1.1

CPU Clock – clk

CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

8.1.2

I/O Clock – clk

I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.

The I/O clock is also used by the External Interrupt module, but note that some external inter-

rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O

clock is halted. Also note that start condition detection in the USI module is carried out asynchro-

nously when clk

I/O is halted, TWI address recognition in all sleep modes.

8.1.3

Flash Clock – clk

FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

General I/O

Modules

Asynchronous

Timer/Counter

CPU Core

RAM

clk

I/O

clk

ASY

AVR Clock

Control Unit

clk

CPU

Flash and

EEPROM

clk

FLASH

Source clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Timer/Counter

Oscillator

Crystal

Oscillator

Low-frequency

Crystal Oscillator

External Clock

ADC

clk

ADC

System Clock

Prescaler

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