ATmega16HVB datasheet(83/273 Pages) ATMEL

83 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

the word. When accessing 16-bit registers, special procedures described in section ”Accessing

Registers in 16-bit Mode” on page 90 must be followed.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment its value. The Timer/Counter is inactive when no clock source is selected. The

output from the Clock Select logic is referred to as the timer clock (clk

Tn).

17.2.2

Definitions

Many register and bit references in this section are written in general form. A lower case “n”

replaces the module number, e.g. Timer/Counter number. A lower case “x” replaces the unit,

e.g. OCRnx and ICPnx describes OCRnA/B and ICP1/0x . However, when using the register or

bit defines in a program, the precise form must be used, i.e., TCNT0L for accessing

Timer/Counter0 counter value and so on.

The definitions in Table 17-1 are also used extensively throughout the document.

17.3

Timer/Counter Clock Sources

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source.

The Clock Select logic is controlled by the Clock Select (CSn2:0) bits located in the Timer/Coun-

ter Control Register n B (TCCRnB), and controls which clock source and edge the

Timer/Counter uses to increment its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk

Tn). For

details on clock sources and prescaler, see ”Timer/Counter0 and Timer/Counter1 Prescalers” on

page 79

17.4

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

17-2 on page 83 shows a block diagram of the counter and its surroundings.

Figure 17-2. Counter Unit Block Diagram

Table 17-1.

Definitions

BOTTOM

The counter reaches the BOTTOM when it becomes 0.

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255) in 8-bit mode or

0xFFFF (decimal 65535) in 16-bit mode.

TOP

The counter reaches the TOP when it becomes equal to the highest value in the count

sequence. The TOP value can be assigned to be the fixed value 0xFF/0xFFFF (MAX) or

the value stored in the OCRnA Register.

DATA BUS

TCNTn

Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

ATmega16HVB Datenblatt(PDF) 83 Page - ATMEL Corporation

ATmega16HVB Datenblatt(HTML) 83 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL