ACE5372

Low Power Real-Time Clock (RTC)

VER 1.2

11

In the 2Hz clock pulse mode, 0.496s clock pulses and 0.504s clock pulses are output alternatively.

Duty cycle for 1Hz clock pulses becomes 50.4%.

2) Level mode: One second, one minute or one month may be selected for an interrupt cycle. Counting up

of seconds is matched with falling edge of interrupt output.

3) When the time trimming circuit is used, periodic interrupt cycle changes every 20 seconds.

Pulse mode:“L” duration of output pulses may change in the maximum range of ±3.784ms (±3.875ms

when 32KHz crystal is used).

For example, Duty will be 50±0.3784% (or 50±0.3875% when 32KHz crystal is used) at 1Hz.

Level Mode: Frequency is one second may change in the maximum range of ±3.784ms (±3.875ms

when 32KHz crystal is used).

Relation Between Mode Waveforms and CRFG Bit

Pulse mode

Level mode

7. Control Register 2 ( at internal address FH )

D7

D6

D5

D4

D3

D2

D1

D0

Operation

-

-

12_/24

ADJ

CLEN_

CTFG

AAFG

BAFG

Write

0

0

12_/24

XSTP

CLEN_

CTFG

AAFG

BAFG

Read

0

0

Undefined

1

0

0

0

0

Default

*The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc.

⎯12/24

⎯12/24-hour Time Display System Selection bit

⎯12/24

Description

0

12-hour time display system

1

24-hour time display system

Being set this bit at “0” indicates 12-hour display system while “1” indicates 24-hour system.