ACE5372

Low Power Real-Time Clock (RTC)

VER 1.2

15

As the arrival of the start condition, master emitter must send out an address command bit, which

includes slave address and R/W model; When a certain receiver in bus is chosen, it will send ACK signal

and SDA changes into low voltage. ACK signal indicates the success of data transmission. When SCL

clock drops, emitter sends continuously 8 bits and releases the data bus (SDA changes into high voltage).

The slave address

The high effective 7 bits (bit7---bit1) in the address byte are defined as device type id. In ACE5372,

these 7 bits are 0110010. The lowest bit0 is defined as R/W model. When this bit is “1”, it is read model,

while “0” is write model.

The slave address

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0

1

1

0

0

1

0

R/W

BIT7-BIT1 : The slave address of the ACE5372 is defined as 0110010

BIT0 : R/W definition

“1” is read model

“0” is write model

Data transmission format in the Interface Communication

Interface generates no Chip Enable signals. In place of it each device has a 7bit slave address

allocated. The first 1byte is allocated to this 7bit of slave address and to the command (R/

⎯W) for which

data transmission direction is designated b the data transmission thereafter.

The slave address of the ACE5372 is specified at (0110010).

At the end of data transmission/receiving stop condition is generated to complete transmission. However,

if start condition is generated without generating stop condition, repeated start condition is met and

transmission/receiving data may be continued by setting the slave address again. Use this procedures

when the transmission direction needs t be changed during one transmission.

Data is written into the slave from the master

S 0 1 1 0 0 1 0

0

A Data A Data A P

Slave address

Write

When data is read from the slave immediately after 7bit addressing from the master

S

0

1 1 0 0 1 0

1

A Data AData A_ P

Slave address

Read