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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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AS3525 Datenblatt(PDF) 65 Page - ams AG |
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AS3525 Datenblatt(HTML) 65 Page - ams AG |
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65 / 194 page  AS3525-A/-B C22O22 Data Sheet, Confidential © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 65 - 194 7.3.9 SPDIF interface As part of the I2SIN module also a SPDIF receiver interface is included. This SPDIF interface works as converter from SPDIF-AES/EBU to I2S. The SPDIF-AES/EBU standard is a serial audio interface that conveys 2 time-multiplexed audio channels, the left and right channels, as is the case in audio stereo transmission. The two channels are encoded in a 64-bit frame. Each individual channel is encoded in a sub-frame that consists of a 4-bit preamble, followed by 24 bits of audio data and 4 control bits, in a total of 32 bits per sub-frame. The SPDIF-AES/EBU standard provides for LSB first, up to 24-bit audio samples, Samples of 20 bits or less may be used, in which case the 4 least significant bits may be used for a 12-bit monitoring channel, transmitted at 1/3 of the sample rate. Please refer to the SPDIF-AES/EBU, AES3 or IEC958 standard documentation for more information. Features • Feed-forward operation: extracts audio data from the SPDIF-AES/EBU input signal by sampling it with a fast clock signal which not necessarily related to the sample rate frequency • Purely digital receiver solution, without need of an input PLL for synchronisation. • The audio samples are output serially in I2S format. • PLL interface to filter out the jitter and generate a jitter-free I2S output. • Recognizes all common audio and video related sample frequencies and outputs a nibble code for each. 7.3.9.1 SPDIF register description Table 48 SPDIF status register Name Base Default I2SIN_SPDIF_STATUS AS3525_I2SIN_BASE 0x00 SPDIF status signals register Offset: 0x0018 This read-only register contains status information of the SPDIF interface. The spdif_sample_freq and spdif_sync status bits are directly derived from the SPDIF converter. In order to provide valid status bits, these signals must be synchronized with pclk, i.e. clk_i2sin. Bit Bit Name Default Access Bit Description 4:1 spdif_sample_freq R Incoming sample frequency 0 spdif_sync R Recognition of sub-frame preamble 0: first sub-frame preamble not recognized 1: successful recognition of the first sub-frame preamble The following table shows the input sample rate in KHz according to the sample_freq_code (bit 5 to 1) in the I2SIN_SPDIF register. sample_freq_code Input Sample Rate (KHz) 0001 22.050 0010 24.000 0011 32.000 0100 44.100 0101 48.000 0110 64.000 0111 88.200 1000 96.000 1001 176.400 1010 192.000 |
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