Production Data

WM2331

WOLFSON MICROELECTRONICS LTD

PD Rev 1.4 April 2001

13

AVDD/2

AIN

REFSENSE

REFTF

REFBF

+FS

-FS

REFTS

REFBS

0.1µF

10µF

0.1µF

0.1µF

VREF

MODE

Figure 11 Differential Mode, 1V Reference Span

AVDD/2

AIN

REFSENSE

+FS

-FS

REFTS

REFBS

VM

VM

DC SOURCE =VM

REFTF

REFBF

0.1µF

0.1µF

0.1µF

10µF

+

-

MODE

Figure 12 Centre Span Mode, 2V Reference Span

TOP/BOTTOM MODE (MODE = AGND)

Top/Bottom mode is enabled by connecting the MODE pin to AVDD. In this mode, the ADC

Reference voltages REFTF and REFBF are generated by the internal reference buffer from the

externally supplied voltages REFTS and REFBS. Only single-ended input is possible in

TOP/BOTTOM Mode.

SAMPLE

AND

HOLD

REFTS

REFBS

AIN

-1/2

+1

-1/2

PGA

REFTF =

AVDD + (REFTS - REFBS)

ADC

CORE

INTERNAL

REFERENCE

BUFFER

REFBF =

AVDD - (REFTS - REFBS)

Figure 13 ADC Reference Generation in Top/Bottom Mode

The voltage difference between REFTS and REFBS should equal the peak-to-peak input signal

amplitude times the PGA gain (see ‘Analogue Signal Path’, above). A smaller voltage difference

would give rise to out-of-range conditions, whereas a larger one would not fully utilise the ADC

Typically, REFSENSE is tied to AVDD to disable the on-chip reference generator, but the user can

also choose to use its output to drive either REFTS or REFBS.