Production Data

WM2331

WOLFSON MICROELECTRONICS LTD

PD Rev 1.4 April 2001

19

APPLICATIONS INFORMATION

DRIVING THE CLOCK INPUT

Obtaining good performance from the WM2331 requires care when driving the clock input.

Different sections of the Sample-and-Hold and ADC operate while the clock is low or high. The user

should ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as

much time as possible in which to operate.

The CLK pin should also be driven from a low jitter source for best dynamic performance. To

maintain low jitter at the CLK input, any clock buffers external to the WM2331 should have fast rising

edges. Use a fast logic family such as AC or ACT to drive the CLK pin, and consider powering any

clock buffers separately from any other logic on the PCB to prevent digital supply noise appearing on

the buffered clock edges as jitter.

As the CLK input threshold is nominally around AVDD/2, any clock buffers need to have an

appropriate supply voltage to drive above and below this level.

DRIVING THE SAMPLE AND HOLD INPUTS

DRIVING THE AIN PIN

Figure 20 shows an equivalent circuit for the WM2331 AIN pin. The load presented to the system at

V

LAST

AIN

AVDD

AGND

CLK

CLK

C

P1

C

Sample

1.2pF

+

-

C

8pF

Figure 20 Equivalent Circuit for Analogue Input Pin AIN

circuit modelled as an equivalent resistor

CLK

S

IN

f

C

R

×

=

1

2

input loading versus source resistance for high impedance sources.

V

AIN

AVDD

AGND

+

-

R

C

I

IN

Figure 21 Equivalent Circuit for the AIN Switched Capacitor Input