Production Data

WM9701A

WOLFSON MICROELECTRONICS LTD.

PD Rev 3.2 January 2001

11

SYNC remains high for a total duration of 16 BIT CLKs at the beginning of each audio frame.

The portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of

the audio frame where SYNC is low is defined as the “Data Phase”. Additionally, for power savings,

all clock, sync, and data signals can be halted. This requires that WM9701A be implemented as a

static design to allow its register contents to remain intact when entering a power savings mode.

AC-LINK AUDIO OUTPUT FRAME (SDATA_OUT)

The audio output frame data streams correspond to the multiplexed bundles of all digital output data

targeting WM9701A’s DAC inputs, and control registers. As briefly mentioned earlier, each audio

output frame supports up to 12, 20-bit outgoing data time slots. Slot 0 is a special reserved time slot

containing 16-bits, which are used for AC-link protocol infrastructure.

Within slot 0 the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the

entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains

at least one time slot of valid data. The next 12-bit positions sampled by WM9701A indicate which of

the corresponding 12 time slots contain valid data.

In this way data streams of differing sample rates can be transmitted across AC-link at its fixed 48

kHz audio frame rate. Figure 8 illustrates the time slot based AC-link protocol.

SYNC

BIT_CLK

SDATA_OUT

WM9701A SAMPLES SYNC ASSERTION

WM9701A SAMPLES FIRST

SDATA_OUT BIT OF FRAME HERE

END OF PREVIOUS AUDIO FRAME

VALID

FRAME

SLOT (1)

SLOT (2)

Figure 9 Start of an Audio Output Frame

A new audio output frame begins with a low to high transition of SYNC as shown in Figure 9. SYNC

is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK,

WM9701A samples the assertion of SYNC. This falling edge marks the time when both sides of AC-

link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, AC’97

transitions SDATA_OUT into the first bit position of slot 0 (“Valid Frame” bit). Each new bit position is

presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the WM9701A on

the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent

sample points for both incoming and outgoing data streams are time aligned.

Baseline AC’97 specified audio functionality MUST ALWAYS sample rate convert to and from a

fixed 48 ks/s on the AC’97 controller.

This requirement is necessary to ensure that interoperability between the AC’97 controller and

WM9701A, among other things, can be guaranteed by definition for baseline specified AC’97

features.

SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slot bit positions

stuffed with 0s by the AC’97 controller.

In the event that there are less than 20 valid bits within an assigned and valid time slot, the AC’97

controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0s.

As an example, consider an 8-bit sample stream that is being played out to one of WM9701A’s

DACs. The first 8-bit positions are presented to the DAC (MSB justified) followed by the next 12-bit-

positions, which are stuffed with 0s by the AC’97 controller. This ensures that regardless of the

resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least

significant bits.

When mono audio sample streams are output from the AC’97 controller, it is necessary that BOTH

left and right sample stream time slots be filled with the same data.