Production Data

WM9701A

WOLFSON MICROELECTRONICS LTD.

PD Rev 3.2 January 2001

19

WRITE BIT

FUNCTION

PR0

PCM in ADCs and input Mux power down

PR1

PCM out DACs power down

PR2

Analogue mixer power down (VREF still on)

PR3

Analogue mixer power down (VREF off)

PR4

Digital interface (AC-Link) power down (external clock off)

PR5

Internal clock disable

PR6

HP amp power down - not supported

PR7

Modem ADC/DAC off - not supported

Table 9 Power Down Control Register Function

PR0 = 1

PR1 = 1

PR2 = 1

PR4 = 1

PR0 = 0 AND

ADC = 1

DEFAULT

READY = 1

COLD RESET

WARM

RESET

PR2 = 0 AND

ANL = 1

PR1 = 0 AND

DAC = 1

ADCs OFF

PR0

DACs OFF

PR1

ANALOGUE

OFF PR2 OR

PR3

DIGITAL I/F

OFF PR4

SHUT OFF

CODA LINK

NORMAL

Figure 12 An Example of WM9701A Power Down/Power up Flow

Figure 12 illustrates one example procedure to do a complete power down of WM9701A. From

normal operation sequential writes to the power down Register are performed to power down

WM9701A a piece at a time. After everything has been shut off, a final write (of PR4) can be

executed to shut down the WM9701A’s digital interface (AC-link).

The part will remain in sleep mode with all its registers holding their static values. To wake up

WM9701A, the AC’97 controller will send a pulse on the sync line issuing a warm reset. This will

restart WM9701A’s digital interface (resetting PR4 to 0). WM9701A can also be woken up with a

cold reset. A cold reset will cause a loss of values of the registers, as a cold reset will set them to

their default states. When a section is powered back on, the power down Control/Status register

(index 26h) should be read to verify that the section is ready (i.e. stable) before attempting any

operation that requires it.

Alternatively if RESETB is held low, all PR bits are held set so the device is held powered off until

RESETB is taken high again.