LPC1313 datasheet(8/60 Pages) NXP

8 / 60 page

LPC1311_13_42_43_2

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Product data sheet

Rev. 02 — 6 May 2010

8 of 60

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

6.2 Pin description

Fig 5.

LPC1311/13 HVQFN33 package

002aae517

LPC1311FHN33

LPC1313FHN33

Transparent top view

PIO0_8/MISO/CT16B0_MAT0

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL/CT16B0_CAP0

PIO0_9/MOSI/CT16B0_MAT1/SWO

VDD

SWCLK/PIO0_10/SCK/CT16B0_MAT2

XTALOUT

PIO1_10/AD6/CT16B1_MAT1

XTALIN

R/PIO0_11/AD0/CT32B0_MAT3

PIO0_1/CLKOUT/CT32B0_MAT2

R/PIO1_0/AD1/CT32B1_CAP0

RESET/PIO0_0

R/PIO1_1/AD2/CT32B1_MAT0

PIO2_0/DTR

R/PIO1_2/AD3/CT32B1_MAT1

terminal 1

index area

33 VSS

Table 3.

LPC1313/43 LQFP48 pin description table

Symbol

Type

Description

RESET/PIO0_0

3[1]

RESET — External reset input: A LOW on this pin resets the device,

causing I/O ports and peripherals to take on their default states, and

processor execution to begin at address 0.

I/O

PIO0_0 — General purpose digital input/output pin.

PIO0_1/CLKOUT/

CT32B0_MAT2/

USB_FTOGGLE

4[2]

I/O

PIO0_1 — General purpose digital input/output pin. A LOW level on this pin

during reset starts the ISP command handler or the USB device

enumeration (USB on LPC1343 only, see description of PIO0_3).

CLKOUT — Clockout pin.

CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

USB_FTOGGLE — USB 1 ms Start-of-Frame signal (LPC1343 only).

PIO0_2/SSEL/

CT16B0_CAP0

10[2]

I/O

PIO0_2 — General purpose digital input/output pin.

SSEL — Slave select for SSP.

CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

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