ADM1025/ADM1025A

Preliminary Technical Data

Rev. P5 | Page 6 of 21| www.onsemi.com

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3.Pin Configuration

Table 3. Pin Function Descriptions

Pin

No.

Mnemonic

Description

1

SDA

Digital I/O. Serial bus bidirectional data. Open-drain output.

2

SCL

Digital Input. Serial bus clock.

3

GND

System Ground

4

Power. Can be powered by 3.3 V standby power if monitoring in low power states is required. This pin also

5

VID0

Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0−VID3 Status

Register. It has an on-chip 100 kΩ pull-up resistor (ADM1025 only).

6

VID1

Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0−VID3 Status

Register. It has an on-chip 100 kΩ pull-up resistor (ADM1025 only).

7

VID2

Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0−VID3 Status

Register. It has an on-chip 100 kΩ pull-up resistor (ADM1025 only).

8

VID3

Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0−VID3 Status

Register. It has an on-chip 100 kΩ pull-up resistor (ADM1025 only).

9

D−/NTI

Analog/Digital Input. Connected to cathode of external temperature sensing diode. If held high at power-up, it

initiates NAND tree test mode.

10

D+

Analog Input. Connected to anode of external temperature sensing diode.

11

VID4 Core Voltage ID readout from the processor. This value is read into the VID4 Status Register. In analog 12

12

Analog Input. Monitors 5 V supply.

13

Analog Input. Monitors 3.3 V supply.

14

Analog Input. Monitors 2.5 V supply.

15

Analog Input. Monitors processor core voltage (0 V to 3.0 V).

16

ADD/RST/INT/NTO

Programmable Digital I/O. The lowest order programmable bit of the SMBus Address, sampled on SMB activity

as a three-state input. Can also be configured to give a minimum 20 ms low reset output pulse. Alternatively, it

can be programmed as an interrupt output for temperature/voltage interrupts. Functions as the output of the

NAND tree in NAND tree test mode.