ADM1025ARQZ-R7 datasheet(18/21 Pages) ONSEMI

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ADM1025/ADM1025A

Preliminary Technical Data

Rev. P5 | Page 18 of 21| www.onsemi.com

REGISTERS

Table 8. Address POINTER Register

Bit

Name

R/W

Description

7–0

Address Pointer

Write

Address of ADM1025/

ADM1025A Registers. See

the tables below for detail.

Table 9. List of Registers

Address

A7–A0

in Hex

Power On Value of

Registers: <7:0>

Configuration

40h

0000 1000

Status Register 1

41h

0000 0000

Status Register 2

42h

0000 0000

VID Register

47h

<7:4> = 0000, <3:0> = VID3–

VID0

VID4 Register

49h

<0> = VID4; Default = 1000

000 (VID4)

Value and Limit

Registers

15–3Dh

Company ID

3Eh

0100 0001

Stepping

3Fh

0010 (Bits 3:0 Version

Number)

Table 10. Register 40h – Configuration Register

Bit

Name

R/W

Description

START

Read/Write

Logic 1 enables startup of

monitor ASIC, and Logic 0

places the ASIC in standby

mode. At startup, limit

checking functions and

scanning begins. Note, all

HIGH and LOW LIMITS should

be set into the ADM1025/

ADM1025A prior to turning

on this bit. (Power-up Default

= 0.)

Reserved

Read

Reserved

Read

Reserved

Read

RESET

Read/Write

Setting this bit generates a

minimum 20 ms low pulse on

Pin 16 if the function is

enabled.

+12/VID4

Select

Read/Write

Selects whether Pin 11 acts

as a 12 V analog input

monitoring pin, or as a VID[4]

input. This pin defaults to the

12 V analog input. (Default =

0.)

Reserved

Read

Initialization

Read/Write

Logic 1 restores power-up

default values to the

Configuration Register and

Status Registers. This bit

automatically clears itself and

the power-on default is zero.

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