STA015 datasheet(28/56 Pages) STMICROELECTRONICS

28 / 56 page

Obsolete

Product(s)

- Obsolete

Product(s)

STA015

28/56

DRB

Address: 0x49 (73)

Type: R/W

Software Reset: 0xFF

Hardware Reset: 0xFF

DRB register is used to re-direct the Right Channel on the Left, or to mix both the Channels. Default value

is 0x00, corresponding at the maximum attenuation in the re-direction channel.

CHIP_MODE

Address: 0x4D (77)

Type: R/W

Hardware Reset: 0x00

Using this register it’s possible to select which operation will be performed by the DSP.

Possible values are:

0x00 - MP3 decoding

0x01 - Reserved

0x02 - ADPCM Encoder

0x03 - ADPCM Decoder

0x04 - BYPASS mode

The DSP will check for the value of this register right after the RUN command has been issued (refer to

RUN register). After that no more checks will be performed: therefore a SOFT_RESET must be generated

in order to change the device mode.

CRCR

Address: 0x4E (78)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

The CRC register is used to enable/disable the CRC check. If CRC_EN bit is cleared, the CRC value en-

coded in the bitstream is checked against the hardware one. If a discrepance occurs, the current frame is

skipped and the decoder is muted. The ERROR_CODE register is affected with the value 0x01.

MSB

LSB

Description

DRB7

DRB6

DRB5

DRB4

DRB3

DRB2

DRB1

DRB0

OUTPUT ATTENUATION

0000

NO ATTENUATION

0000

-1dB

0000

-2dB

::::

1100

-96dB

MSB

LSB

XXXX

CRCEN

STA015 Datenblatt(PDF) 28 Page - STMicroelectronics

STA015 Datenblatt(HTML) 28 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datenblatt Download

Link URL