M41T94 datasheet(23/41 Pages) STMICROELECTRONICS

23 / 41 page

M41T94

Clock operations

23/41

Figure 13.

RSTIN1 and RSTIN2 timing waveforms

4.8

Calibrating the clock

The M41T94 is driven by a quartz-controlled oscillator with a nominal frequency of

32,768 Hz. Uncalibrated clock accuracy will not exceed ±35 ppm (parts per million)

oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. When

the Calibration circuit is properly employed, accuracy improves to better than ±2 ppm at

25°C.

The oscillation rate of crystals changes with temperature (see Figure 14 on page 25).

Therefore, the M41T94 design employs periodic counter correction. The calibration circuit

adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as

shown in Figure 15 on page 25. The number of times pulses are blanked (subtracted,

negative calibration) or split (added, positive calibration) depends upon the value loaded into

the five calibration bits found in the control register. Adding counts speeds the clock up,

subtracting counts slows the clock down.

The calibration bits occupy the five lower order bits (D4-D0) in the control register (8h).

These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a

sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs

within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one

second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is

loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a

binary 6 is loaded, the first 12 will be affected, and so on.

Table 7.

Reset AC characteristics(1)

Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5 V (except where noted).

Symbol

Parameter

Min

Max

Unit

tRLRH1

(2)

Pulse width less than 50 ns will result in no RESET (for noise immunity).

RSTIN1 low to RSTIN1 high

200

tRLRH2

(3)

Pulse width less than 20 ms will result in no RESET (for noise immunity).

RSTIN2 low to RSTIN2 high

100

tR1HRH

(4)

Programmable (see Table on page 27).

RSTIN1 high to RST high

200

tR2HRH

(4)

RSTIN2 high to RST high

200

AI03665

RSTIN2

RST

(1)

RSTIN1

tRLRH1

tRLRH2

tR1HRH

tR2HRH

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