SA9101 datasheet(20/40 Pages) SAMES

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Detailed Description

ADR 0

ALARM Control

Bit

Description

Name

CR0B0

Alarm simulation

A “1” initiates error simulation of alarm indication signal

(AIS), slip, parity, CRC, no signal, loss of frame alignment,

remote alarm, code violations and framing errors.

Error counters for frame errors, code violations and CRC

errors will be incremented.

CR0B1

Force re-synchronisation

Setting of this bit initializes resynchronisation to establish

normal frame alignment and, if enabled, CRC4 frame re-

synchronization.Resetting is not necessary.

CR0B2

Clear CHNL Parity Alarm Latch

Setting of this bit forces reset of CHNL Parity error alarms.

Status-registers ADR 0, bit 2 and ADR 5, bit 3, 4 will be reset

to “0”.

CR0B3

Send AIS towards System interface (DRO), i.e. switching

network (SN). Device sends AIS (continuously one’s) to the

SN. Tests of the speech memory in loopback mode are not

effected.

CR0B4

Disable Error Counters

This bit can be set 1µs before the contents of the error

counters are read to get stable values. The error counters

will be reset after this bit is reset to zero. No errors are

counted while this bit is active. This procedure has been

implemented to maintain compatibility with the previous

frame aligners. If an error counter is read without setting this

bit previously, only the adressed error - counter will be reset

after read -access has been completed.

CR0B5

Enable Control Registers Read

If this bit is set to one, the control registers (ADR0-ADRD) are

selected instead of the status registers during read operation.

CR0B6

Enable Full HDB3-Error Detection

This bit enables HDB3 check for groups of more than 3

spaces (zeros)

CR0B7

Enable Alarm Interrupt Mode

Output DFPY changes its function to AINT while this bit is at

"1”.

Note:

All "Not used" bits must be set to zero in all control registers

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