SA9101 datasheet(25/40 Pages) SAMES

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SA9101

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ADR 8

Receive Control 0

Bit

Description

Name

CR8B[0-2]

0-2

Set value which is loaded into the receive bit counter when the

synchronization pulse is active

CR8B3

Receive Data Input Sense

Bit at “0” :

Dual rail inputs are active low; optical input is

active high

Bit at “1” :

Dual rail inputs are active high; optical output

is active low

CR8B4

Not used

CR8B5

Not used

CR8B6

Receive Parity Type

0 : Even

1 : Odd

CR8B7

Enable CRC Error Counter Extension

Bit at “0” : 8 bit counter

Bit at “1” : 10 bit counter

Note: Receive Data Input Sense is only required for SR6B6 function. HDB3 is

insensitive to polarity.

ADR 9

Receive Control 1

Bit

Description

Name

CR9B[0-5]

0-5

Set value for timeslot which is loaded into the receive counter

when the synchronization pulse is active

CR9B[6-7]

6-7

Not used (fixed to “1”)

ADR A

Transmit Signalling Stack (2 byte FIFO)

Bit

Description

Name

CRAB[0-7]

0-7

Data for timeslot 16

Previous byte will be repeated, if not updated after request.

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