R8C datasheet(5/50 Pages) RENESAS

5 / 50 page

REJ03B0320-0010 Rev.0.10

Page 5 of 47

Jul 12, 2010

R8C/3JT Group

1. Overview

Under development Preliminary document

Specifications in this document are tentative and subject to change.

1.3

Block Diagram

Figure 1.2 shows a Block Diagram.

Figure 1.2

Block Diagram

R8C CPU core

Memory

ROM (1)

RAM (2)

Multiplier

R0H

R0L

R1H

R1L

USP

ISP

INTB

FLG

I/O ports

Notes:

1. ROM size varies with MCU type.

2. RAM size varies with MCU type.

Port P1

Port P3

Port P4

Port P0

Port P2

Peripheral functions

Timers

Timer RA (8 bits

× 1)

Timer RB (8 bits

× 1)

Timer RC (16 bits

× 1)

Watchdog timer

(14 bits)

A/D converter

(10 bits

× 12 channels)

System clock generation

circuit

XIN-XOUT

High-speed on-chip oscillator

Low-speed on-chip oscillator

Voltage detection circuit

DTC

Low-speed on-chip oscillator

for watchdog timer

UART or

clock synchronous serial I/O

(8 bits

× 2)

LIN module

Sensor Control Unit

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