ST6285B datasheet(43/78 Pages) STMICROELECTRONICS

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ST62T85B/E85B

4.3 AUTO-RELOAD TIMER

The Auto-Reload Timer (AR Timer) on-chip pe-

ripheral consists of an 8-bit timer/counter with

compare and capture/reload capabilities and of a

7-bit prescaler with a clock multiplexer, enabling

the clock input to be selected as fINT, fINT/3. A

Mode Control Register, ARMC, two Status Control

Registers, ARSC0 and ARSC1, allow the Auto-

Reload Timer to be used in 2 modes:

– Auto-reload mode,

– Output compare,

The AR Timer can be used to wake the MCU from

WAIT mode with an internal clock. A Load register

allows the program to read and write the counter

on the fly.

4.3.1 AR Timer Description

The AR COUNTER is an 8-bit up-counter incre-

mented on the input clock’s rising edge. The coun-

ter is loaded from the ReLoad/Capture Register,

ARRC, for auto-reload operations, as well as for

initialization. Direct access to the AR counter is not

possible; however, by reading or writing the ARLR

load register, it is possible to read or write the

counter’s contents on the fly.

The AR Timer’s input clock can be either the inter-

nal clock (from the Oscillator Divider), or the inter-

nal clock divided by 3. Selection between these

clock sources is effected by suitably programming

bits CC0-CC1 of the ARSC1 register. The output

of the AR Multiplexer feeds the 7-bit programma-

ble AR Prescaler, ARPSC, which selects one of

the 8 available taps of the prescaler, as defined by

PSC0-PSC2 in the AR Mode Control Register.

Thus the division factor of the prescaler can be set

to 2n (where n = 0, 1,..7).

The clock input to the AR counter is enabled by the

TEN (Timer Enable) bit in the ARMC register.

When TEN is reset, the AR counter is stopped and

the prescaler and counter contents are frozen.

When TEN is set, the AR counter runs at the rate

of the selected clock source. The counter is

cleared on system reset.

The AR counter may also be initialized by writing

to the ARLR load register, which also causes an

immediate copy of the value to be placed in the AR

counter, regardless of whether the counter is run-

ning or not. Initialization of the counter, by either

method, will also clear the ARPSC register, where-

upon counting will start from a known value.

4.3.2 Timer Auto-reload Operating Modes

The free running 8-bit counter is fed by the pres-

caler’s output, and is incremented on every rising

edge of the clock signal.

When a counter overflow occurs, the counter is

automatically reloaded with the contents of the Re-

load/Capture Register, ARCC. The period be-

tween two overflows is then controlled by the pres-

caler setting and by the auto-reload value present

in the Reload/Capture register, ARRC.

On overflow, the OVF flag of the ARSC0 register is

set and an overflow interrupt request is generated

if the overflow interrupt enable bit, OVIE, in the

Mode Control Register (ARMC), is set. The OVF

flag must be reset by the user software.

When the counter reaches the compare value, the

CPF flag of the ARSC0 register is set and a com-

pare interrupt request is generated, if the Compare

Interrupt enable bit, CPIE, in the Mode Control

Notes. The compare value loaded in the Compare

RC) to 255.

The ARTC counter is initialized by writing to the

ARRC register and by then setting the TCLD (Tim-

er Load) and the TEN (Timer Clock Enable) bits in

the Mode Control register, ARMC.

Enabling and selection of the clock source is con-

trolled by the CC0, CC1, SL0 and SL1 bits in the

Status Control Register, ARSC1. The prescaler di-

vision ratio is selected by the PS0, PS1 and PS2

bits in the ARSC1 register.

The clock frequency should not be modified while

the counter is counting, since the counter may be

set to an unpredictable value. For instance, the

multiplexer setting should not be modified while

the counter is counting.

Loading of the counter by any means (by auto-re-

load, through ARLR, ARRC or by the Core) resets

the prescaler at the same time.

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