5000 datasheet(31/104 Pages) INTEL

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Dual-Core Intel® Xeon® Processor 5000 Series Datasheet

Electrical Specifications

Notes:

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

All outputs are open drain.

VHYS represents the amount of hysteresis, nominally centered about 0.5 * VTT for all PWRGOOD and TAP

inputs.

PWRGOOD input and the TAP signal group must meet system signal quality specification in Section 3.

The maximum output current is based on maximum current handling capability of the buffer and is not

specified into the test load.

Notes:

1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.All outputs are open drain.

3.VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

4.VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5.VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal

quality specifications in Section 3.

6.Refer to the processor HSPICE* I/O Buffer Models for I/V characteristics.

7.The VTT referred to in these specifications refers to instantaneous VTT.

8.The maximum output current is based on maximum current handling capability of the buffer and is not

specified into the test load.

9.Leakage to VSS with land held at VTT.

10.Leakage to VTT with land held at 300 mV.

11.LINT0/INTR and LINT1/NMI use GTLREF_ADD as a reference voltage. For these two signals VIH =

GTLREF_ADD + (0.10 * VTT) and VIL= GTLREF_ADD - (0.10 * VTT).

2.12.1

VCC Overshoot Specification

The Dual-Core Intel Xeon Processor 5000 series can tolerate short transient overshoot

events where VCC exceeds the VID voltage when transitioning from a high-to-low

current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the

ILI

Input Leakage Current

N/A

± 200

µA

ILO

Output Leakage Current

N/A

± 200

µA

RON

Buffer On Resistance

Table 2-14. PWRGOOD Input and TAP Signal Group DC Specifications (Sheet 2 of 2)

Symbol

Parameter

Min

Max

Unit

Notes 1,

Table 2-15. GTL+ Asynchronous and AGTL+ Asynchronous Signal Group

DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes1

VIL

Input Low Voltage

0.0

(0.5 * VTT) - (0.10 * VTT)

3, 11

VIH

Input High Voltage

(0.5 * VTT) + (0.10 * VTT)VTT

4, 5, 7,

VOH

Output High Voltage

0.90*VTT

VTT

V2, 5, 7

IOL

Output Low Current

VTT/

[(0.50*RTT_MIN)+(RON_MIN)]

ILI

Input Leakage Current

N/A

± 200

µA

ILO

Output Leakage

Current

N/A

± 200

µA

RON

Buffer On Resistance

Table 2-16. VTTPWRGD DC Specifications

Symbol

Parameter

Min

Max

Unit

VIL

Input Low Voltage

0.0

0.30

VIH

Input High Voltage

0.90

VTT

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