PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

© 1999 SEMTECH CORP.

PRELIMINARY - December 2, 1999

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1186

11

)

1

(

R

I

P

)

on

(

DS

2

O

COND

δ

−

⋅

⋅

=

FET type

R

P

Package

IRL34025

15

1.69

D

IRL2203

10.5

1.19

D

Si4410

20

2.26

SO-8

FET type

R

P

Package

IRL34025

15

1.33

D

IRL2203

10.5

0.93

D

Si4410

20

1.77

SO-8

BOTTOM FET - Bottom FET losses are almost entirely

due to conduction. The body diode is forced into con-

duction at the beginning and end of the bottom switch

conduction period, so when the FET turns on and off,

there is very little voltage across it, resulting in low

switching losses. Conduction losses for the FET can be

determined by:

For the example above:

Each of the package types has a characteristic thermal

impedance, for the TO-220 package, thermal

impedance is mostly determined by the heatsink used.

For the surface mount packages on double sided FR4, 2

oz printed circuit board material, thermal impedances of

40

readily achievable. The corresponding temperature rise

is detailed below:

Temperature rise (

FET type

Top FET

Bottom FET

IRL34025

67.6

53.2

IRL2203

47.6

37.2

Si4410

180.8

141.6

It is apparent that single SO-8 Si4410 are not adequate

for this application, but by using parallel pairs in each po-

sition, power dissipation will be approximately halved and

temperature rise reduced by a factor of 4.

INPUT CAPACITORS - since the RMS ripple current

in the input capacitors may be as high as 50% of the

output current, suitable capacitors must be chosen ac-

cordingly. Also, during fast load transients, there may

be restrictions on input di/dt. These restrictions require

useable energy storage within the converter circuitry,

either as extra output capacitance or, more usually,

additional input capacitors. Choosing low ESR input

capacitors will help maximize ripple rating for a given

size.

SHORT CIRCUIT PROTECTION - LINEARS

The Short circuit feature on the linear controllers is

implemented by using the Rds(on) of the FETs. As

output current increases, the regulation loop maintains

the output voltage by turning the FET on more and

more. Eventually, as the Rds(on) limit is reached, the

FET will be unably to turn on more fully, and output

voltage will start to fall. When the output voltage falls

to approximately 50% of nominal, the LDO controller

is latched off, setting output voltage to 0. Power must

be cycled to reset the latch.

To prevent false latching due to capacitor inrush cur-

rents or low supply rails, the current limit latch is ini-

tially disabled. It is enabled at a preset time (nominally

2mS) after both the LDOV and LDOEN rails rise

above their lockout points.

To be most effective, the linear FET Rds(on) should

not be selected artificially low, the FET should be cho-

sen so that, at maximum required current, it is almost

fully turned on

If, for example, a linear supply of 1.5V at 4A is re-

quired from a 3.3V ± 5% rail, max allowable Rds(on)

would be.

Rds(on)max = (0.95*3.3-1.5)/4

≈ 400mΩ

To allow for temperature effects 200m

Ω would be a

suitable room temperature maximum, allowing a peak

short circuit current of approximately 15A for a short

time before shutdown.

Using 1.5X Room temp R

rise.