SM5K3 datasheet(16/28 Pages) SHARP

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SM5K3/SM5K4/SM5K5

- 16 -

• Interrupt used with SM5K3/5K4/5K5

Interrupt event occurs on the falling edge of P10 or

P11 pin input, or the overflow at the timer. These

events set flags IFA, IFB and IFT respectively, that

then serve as interrupt request flag.

Table 4 shows interrupt handling priority level and

jump address.

Table 4

Interrupt Event Summary

INTERRUPT EVENT

(REQUEST FLAG)

JUMP ADDRESS

PRIORITY ORDER

INTERRUPT MASK FLAG

Falling edge of input on P10 (IFA)

RE0

Falling edge of input on P11 (IFB)

RE1

Timer overflow (IFT)

RE2

PAGE

STEP

• Usage of halt mode and stop mode

The system returns back to the normal operation

mode upon occurring of a standby mode releasing

condition. The halt mode should be used when the

system must enter and exit normal operation

frequently as in the case of key operation.

The halt mode should also be used to keep timers

that are operating from the internal clock, while in

the standby mode.

The stop mode further saves power than the halt

mode but requires slightly longer time to return to

the normal mode. Therefore, the stop mode should

be used when the system will not be required to

return to the normal mode in a short time.

Interrupt Feature

The interrupt block consists of mask flags (bits RE0,

RE1 and RE2), IME flag and interrupt request

handling circuit. Fig. 9 shows the configuration of the

interrupt block.

Mask flag (mode register RE)

RE2

I FA

I FB

I FT

RE1

RE0

Interrupt request flag

IME

Interrupt enable flag

(master enable flag)

Interrupt handling circuit

INT signal

Stack register SR

Program counter PC

Fig. 9

Interrupt Block Diagram

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