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SM5K3 Datenblatt(PDF) 23 Page - Sharp Corporation |
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SM5K3 Datenblatt(HTML) 23 Page - Sharp Corporation |
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23 / 28 page ![]() - 23 - INSTRUCTION SET Definition of Symbols M : Content of RAM at the address defined by the B register. ← : Transfer direction ∪ : Logical OR ∩ : Logical AND ⊕ : Exclusive OR Ai : An i bit of A register (i = 3 to 0) Push : Saves the contents of PC to stack register SR. Pop : Returns the contents saved in the stack register back to PC. Pj : Indicates output latch register or input register. Pj ( j = 0, 1, 2, 3, 4, 5) Rj : Mode register. Rj register ( j = 3, A, B, C, E, F) ROM ( ) : Content stored in ROM location defined by the value in ( ). CY : Carry in ALU (independent of C flag) The CY(carry) is a signal which is generated when the ALU has been carried by the execution of a command. It is different from the C flag. X : Used to represent a group of bits in the content of a register or memory. For example, the X in the LDAX instruction denotes the lower 2 digits (I1 and I0) of A register. • A bit in a register is affixed to the register symbol, e.g. a bit (i = 0, 1, 2, 3....) of X register is expressed as Xi and P (R) register as P (R) i. • Increment means binary addition of 1H and decrement addition of FH. • Skipping an instruction means to ignore that instruction and to do nothing until starting the next instruction. In this sense, an instruction to be skipped is treated as an NOP instruction. Skipping 1-byte instruction requires 1-cycle, and 2-byte instruction 2-cycle. Skipping 1-byte 2-cycle instruction requires 1-cycle. SM5K3/SM5K4/SM5K5 MNEMONIC MACHINE CODE OPERATION ROM Addressing Instructions TR x 80 to BF PL ←x (I5-I0) TL xy E0 to E7, 00 to FF PU ←x (I11-I6) PL ←y (I5-I0) TRS x C0 to DF Push, PU ←01H, PL ←x (I4, I3, I2, I1, I0) CALL xy F0 to F7 00 to FF Push, PU ←x (I11-I6) PL ←y (I5-I0) RTN 7D Pop RTNS 7E Pop, Skip the next step RTNI 7F Pop, IME ←1 Data Load Instructions LAX x 10 to 1F A ←x (I3-I0) LBMX x 30 to 3F BM ←x (I3-I0) LBLX x 20 to 2F BL ←x (I3-I0) LDA x 50 to 53 A ←M, BMi←BMi ⊕ x (I1, I0), (i = 1, 0) EXC x 54 to 57 M ↔A, BMi←BMi ⊕ x (I1, I0), (i = 1, 0) EXCI x 58 to 5B M ↔A, BL←BL+1 BMi ←BMi ⊕ x (I1, I0), (i = 1, 0) Skip the next step, if result of BL = 0 EXCD x 5C to 5F M ↔A, BL←BL–1 BMi ←BMi ⊕ x (I1, I0), (i = 1, 0) Skip the next step, if result of BL is = FH EXAX 64 A ↔X-reg ATX 65 X-reg ←A EXBM 66 BM ↔A EXBL 67 BL ↔A EX 68 B ↔SB Instruction Summary |
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