THS8200IPFPEP datasheet(29/104 Pages) TI1

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1023

964

817.3 mV

770.0 mV

255

767

511

Input Digital Codes

Ramping Analog Output With 1:1.1 AC Range Fine Scaling

Range After

Scaling Up 1:1.1

700.0 mV

876

DC Shifted

Original AC Range

THS8200-EP

www.ti.com

SLES253 – DECEMBER 2009

Figure 4-7. Effect of Scaling the Analog Video Output

Figure 4-7 illustrates a shifted analog ramping output. The multiplication factor could be calculated to scale

this output range to the full 10-bit range of the DAC. Note that this scaling can be programmed individually

per channel using registers csm_mult_<gy,rcr,bcb>. The range of the multiplication is 0..1.999, coded as a

binary weighted 11-bit value, thus: csm_mult_<gy,rcr,bcb> = (Desired scale ( 0 to 1.999) / 1.999) × 2047.

Note that this approach allows to scale input code ranges that are different on each channel to an identical

full-scale DAC output compliance, as is required for ITU-R.BT601 sampled signals where Y video data is

represented in the range [64..940] and both Cb,Cr color difference channels are coded within the range

[64..960]. All three channels need to generate a 700-mV nominal analog output compliance. Using a

combination of FSADJ—adjusting the full-scale current of all DAC channels simultaneously in the analog

domain—and digital CSM control, different trade-offs can be made for DAC output amplitude control,

including channel matching.

As discussed in Display Timing Generator (Section 4.7), the user also controls the DAC output levels

during blanking, negative and positive sync, pre- and post-equalization, and serration pulses. Using a

combination of CSM and DTG programming, it is therefore possible to accommodate many video

standards, including those that require a video blank-to-black level setup, as well as differing video/sync

ratios (e.g., 10:4 or 7:3).

Finally, using the selectable full-scale adjustment from the FSADJ1 or FSADJ2 terminals, it is possible to

switch between two analog output compliance settings with no hardware changes.

Physically, the CSM output is represented internally as an 11-bit value to improve the DAC linearity at the

10-bit level after scaling. Each DAC internally is of 11-bit resolution.

4.6

Interpolating Finite Impulse Response Filter (IFIR)

For relaxing the requirements of the reconstruction filter behind the DAC in the analog domain, and in

order to take advantage of the high-speed capability of the DACs in THS8200, a 2× digital up-sampling

and interpolation filter module is integrated.

Figure 4-8 through Figure 4-11 show the YRGB and CbCr filtering requirements for HDTV

(SMPTE274M/296M standards) and SDTV (ITU-R.BT601 standard), respectively.

Detailed Functional Description

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