THS8200IPFPEP datasheet(91/104 Pages) TI1

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f - Frequency - MHz

100

200

300

400

500

V = 700 mV

VIO = 3.3 V

V(BIAS) = 350 mV

DLL

Bypassed

DLL Used

160

200

THS8200-EP

www.ti.com

SLES253 – DECEMBER 2009

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

DAC output current

tfi

10 to 90% of full-scale, CLK = 80 MHz

3.5

4.2

fall time

Analog output

Measured from falling edge of CLKIN to 50%

6.5

delay

of full-scale transition(9)

Analog output

Measured from 50% of full scale transition on output to output

tsa

6.6

settling time

settling, within 2%(10)

1 MHz,

−1 dB FS digital sine input

–55

Spurious-free

SFDR

dynamic range

10 MHz,

−1 dB FS digital sine input

–43

Bandwidth (3 dB)

MHz

Eglitch

Glitch energy

Full-scale code transition at 205 MSPS

pVs

(9)

This value excludes the digital process delay, tD(D). Limit from characterization only. Data is clocked in on the rising edge of CLKIN.

Analog outputs become available on the falling edge of CLKIN.

(10) Limit from characterization only.

7.4

Power Requirements

7.4.1

Power for 700-mV DAC Output Compliance + 350-mV Bias at AVDD = 3.3 V,

DVDD = 1.8 V, VDD_IO = 3.3 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels

POWER (mW),

f (MHz)

IAVDD (mA)

IDVDD (mA)

IVDD_IO (mA)

IVDD_DLL (mA)

DLL BYPASSED

DLL USED

329.91

332.88

93.2

10.4

1.1

0.9

338.52

351.72

93.2

1.2

382.47

399.63

93.2

38.5

1.7

5.2

160

450.51

93.2

75.2

2.3

200

476.01

93.2

2.5

Figure 7-1. POWER vs FREQUENCY

7.4.2

Power for 700-mV DAC Output Compliance + 350-mV Bias at AVDD = 3.3 V,

Electrical Characteristics

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