OPA820-HT

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SBOS587

– DECEMBER 2011

Driving Capacitive Loads

One of the most demanding, and yet very common, load conditions for an operational amplifier is capacitive

loading. A high-speed, high open-loop gain amplifier like the OPA820 can be very susceptible to decreased

stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. In simple

terms, the capacitive load reacts with the open-loop output resistance of the amplifier to introduce an additional

pole into the loop and thereby decrease the phase margin. This issue has become a popular topic of application

notes and articles, and several external solutions to this problem have been suggested. When the primary

considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most

effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor

between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response,

but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from

the capacitive load pole, thus increasing the phase margin and improving stability.

at the load. The criterion for setting the recommended resistor is maximum bandwidth, flat frequency response at

the load. Since there is now a passive low-pass filter between the output pin and the load capacitance, the

response at the output pin itself is typically somewhat peaked, and becomes flat after the roll-off action of the RC

network. This is not a concern in most applications, but can cause clipping if the desired signal swing at the load

is very close to the amplifier

’s swing limit. Such clipping would be most likely to occur in pulse response

applications where the frequency peaking is manifested as an overshoot in the step response.

Parasitic capacitive loads greater than 2 pF can begin to degrade the performance of the OPA820. Long PC

board traces, unmatched cables, and connections to multiple devices can easily cause this value to be

exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to

the OPA820 output pin (see the Board Layout section).

Distortion Performance

The OPA820 is capable of delivering an exceptionally low distortion signal at high frequencies and low gains.

The distortion plots in the Typical Characteristics show the typical distortion under a wide variety of conditions.

Most of these plots are limited to 100-dB dynamic range. The OPA820 distortion does not rise above

−90 dBc

until either the signal level exceeds 0.9 V and/or the fundamental frequency exceeds 500 kHz. Distortion in the

audio band is

≤ −100 dBc.

Generally, until the fundamental signal reaches very high frequencies or powers, the 2nd-harmonic will dominate

the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load

impedance improves distortion directly. Remember that the total load includes the feedback network

—in the

Figure 2). Increasing the output voltage swing increases harmonic distortion directly. Increasing the signal gain

will also increase the 2nd-harmonic distortion. Again, a 6-dB increase in gain will increase the 2nd- and

3rd-harmonic by 6 dB even with a constant output power and frequency. Finally, the distortion increases as the

fundamental frequency increases because of the roll-off in the loop gain with frequency. Conversely, the

distortion will improve going to lower frequencies down to the dominant open-loop pole at approximately

100 kHz. Starting from the

Typical Characteristics), the 2nd-harmonic distortion will not show any improvement below 100 kHz and will then

be:

−100 dB − 20 log (1 MHz/100 kHz) = −105 dBc

Copyright

© 2011, Texas Instruments Incorporated

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