4kT

R

R

R

R

G

G

F

S

OPA820

I

BI

E

O

I

BN

4kT = 1.6E − 20J

at 290 K

E

RS

E

NI

√4kTR

S

√4kTR

F

=

+

+

+

+

O

NI

BN

S

S

BI

F

F

2

2

2

2

E

[E

(I R )

4kTR ]NG

(I R )

4kTR NG

æ

ö

=

+

+

+

+

ç

÷

è

ø

BI

F

F

N

NI

BN

S

S

2

2

2

E

I R

4kTR

E

(I R )

4kTR

NG

NG

OPA820-HT

SBOS587

– DECEMBER 2011

www.ti.com

Noise Performance

The OPA820 complements its low harmonic distortion with low input noise terms. Both the input-referred voltage

noise and the two input-referred current noise terms combine to give a low output noise under a wide variety of

operating conditions. Figure 12 shows the operational amplifier noise analysis model with all the noise terms

included. In this model, all the noise terms are taken to be noise voltage or current density terms in either nV/

√Hz

or pA/

√Hz.

Figure 12. Operational Amplifier Noise Analysis Model

The total output spot noise voltage is computed as the square root of the squared contributing terms to the

output noise voltage. This computation is adding all the contributing noise powers at the output by superposition,

then taking the square root to get back to a spot noise voltage. Equation 7 shows the general form for this output

noise voltage using the terms presented in Figure 12.

(7)

voltage at the noninverting input, as shown in Equation 8.

(8)

Evaluating these two equations for the OPA820 circuit presented in Figure 2 will give a total output spot noise

voltage of 6.44 nV/

√Hz and an equivalent input spot noise voltage of 3.22 nV/√Hz.

DC Offset Control

The OPA820 can provide excellent DC signal accuracy because of its high open-loop gain, high common-mode

rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full

advantage of this low input offset voltage, careful attention to input bias current cancellation is also required. The

high-speed input stage for the OPA820 has a moderately high input bias current (9

μA typ into the pins) but with

a very close match between the two input currents

—typically 100-nA input offset current. The total output offset

voltage may be considerably reduced by matching the source impedances looking out of the two inputs. For

example, one way to add bias current cancellation to the circuit of Figure 2 would be to insert a 175-

Ω series

resistor into the noninverting input from the 50-

Ω terminating resistor. When the 50-Ω source resistor is

DC-coupled, this will increase the source impedance for the noninverting input bias current to 200

Ω. Since this is

bias currents to the output leaving only the offset current times the feedback resistor as a residual DC error term

at the output. Using a 402-

Ω feedback resistor, this output error will now be less than ±0.4 μA × 402 Ω = ±160 μV

at 25

°C.

26

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© 2011, Texas Instruments Incorporated

Product Folder Link(s): OPA820-HT