L6360 datasheet(26/65 Pages) STMICROELECTRONICS

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Device configuration

L6360

26/65

Doc ID 022817 Rev 2

Bit 3 = LOL:

L+ overload

This bit is set if a cutoff occurs on the L+ driver.

It is reset after a successful current read if the restart delay time (trcol)

has elapsed or the protection is latched (bit trcol = 1 in Control register 2).

The read operation should begin after the LOL bit has been set. See also

the Control register 2 and Transceiver sections.

When LOL bit is high, IRQ is generated.

When LOL bit is high and the protection is latched (bit trcol = 1 in

Control register 2), the L+ power output is disabled.

The behavior is the same as the C/Q driver (see Figure 12).

Bit 2 = not used: always at zero

Bit 1 = REG LN: Linear regulator undervoltage fault

This bit is set in case of undervoltage of the linear regulator output

(VREGLNL). It is reset after a successful current read if the linear

regulator output has returned to normal operation and the read operation

has begun after the bit has been set.

When REG LN bit is high, IRQ is generated.

Bit 0 = PE:

Parity check error

This flag is set if parity error occurs.

Control register 1

Read/write

Reset value: [00100001]

Figure 13.

Control register 1

The control register holds the parameters to control the L6360. See also the Transceiver

section.

Bit 7 = ENCGQ:

C/QI pull-down enable

Table 13.

ENCGQ: C/Q pull-down enable

ENCGQ

Pull-down generator status

0Always OFF

If ENC/Q = 0

If ENC/Q = 1

OFF

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