L6360 datasheet(46/65 Pages) STMICROELECTRONICS

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Device configuration

L6360

46/65

Doc ID 022817 Rev 2

2nd ÷ 8th frame

Bit 7÷0:

Data register

9th frame

Bit 7÷0:

Microcontroller parity register

The microcontroller parity check (for each register) calculus performed is shown below:

Figure 29.

Microcontroller parity check calculus

Bit 6 = P6:

Microcontroller configuration register parity

This bit is the parity of the configuration register.

Bit 5 = P5:

Microcontroller control register 1 parity

This bit is the parity of control register 1.

Bit 4 = P4:

Microcontroller control register 2 parity

This bit is the parity of control register 2.

Bit 3 = P3:

Microcontroller LED1 register high parity

This bit is the parity of the LED1 MSB register (15 down to 8).

Bit 2 = P2:

Microcontroller LED1 register low parity

This bit is the parity of the LED1 LSB register (7 down to 0).

Bit 1 = P1:

Microcontroller LED2 register high parity

This bit is the parity of the LED2 MSB register high (15 down to 8).

Bit 0 = P0:

Microcontroller LED2 register low parity

This bit is the parity of the LED2 LSB register high (7 down to 0).

For each register, a parity check is calculated as shown in Equation 3, in general formulas:

Equation 3

PX = D7

⊕ D6 ⊕ D5 ⊕ D4 ⊕ D3 ⊕ D2 ⊕ D1⊕ D0 (X = 0 to 6)

D7 ÷ D0 indicates bits inside each register.

If parity error occurs, the registers are not overwritten.

In this writing mode, all writable registers and the microcontroller parity register are sent.

Table 28.

Sequential Write mode direction bit

Master

Slave

Write mode

Read mode

Write mode

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